The present invention relates to level shift circuits for translating logic levels, and more particularly relates to level shift circuits configured to operate at low voltage with reduced power dissipation.
A conventional level shift circuit disclosed in Japanese Patent Publication of examined application Gazette No. 4-40798 has been known. FIG. 14 illustrates the configuration of the conventional level shift circuit.
The level shift circuit shown in FIG. 14 includes two N-type transistors N5 and N6, two cross-coupled P-type transistors P1 and P2, and first and second inverters INV1 and INV2. Each P-type transistor P1 or P2 has its gate connected to the drain of the other. The first inverter INV1 includes an N-type transistor N13 and a P-type transistor P11. The source of the N-type transistor N13 is grounded, while the source of the P-type transistor P11 is connected to a low-voltage supply VDD. The first inverter INV1 is formed by connecting the drains of these transistors with each other and their gates with each other. Likewise, the second inverter INV2 includes an N-type transistor N14 whose source is grounded, and a P-type transistor P12 whose source is connected to the low-voltage supply VDD. The second inverter INV2 is formed by connecting the drains of these transistors with each other and their gates with each other. The first inverter INV1 inverts an input signal received at an input terminal IN, while the second inverter INV2 inverts an inverted signal output from the inverter INV1. The first and second inverters INV1 and INV2 operate powered by the low-voltage supply VDD whose supply voltage is 1.5 V, for example.
All of the devices other than the first and second inverters INV1 and INV2 are high-voltage devices that operate at a high voltage, e.g., 3.3 V, supplied from a high-voltage supply VDD3. The two N-type transistors N5 and N6 receive mutually complimentary signals at their respective sources. More specifically, the source of the N-type transistor N5 receives the inverted version of an input signal from the first inverter INV1, while the source of the N-type transistor N6 receives a signal at the same level as that of the input signal by way of the first and second inverters INV1 and INV2. The gates of the N-type transistors N5 and N6 are connected to the low-voltage supply VDD. The sources of the P-type transistors P1 and P2 are connected to the high-voltage supply VDD3, while their respective drains are connected to the respective drains of the N-type transistors N5 and N6. The connecting point, at which the N-type transistor N6 and the P-type transistor P2 are joined, is connected to an output terminal OUT.
Next, operation of the level shift circuit will be described. When an input signal is at the H level (i.e., the voltage level of the low-voltage supply VDD) and the inverted version of the input signal is at the L (i.e., VSS=0 V) level, the N-type transistor N5 is on, the N-type transistor N6 is off, the P-type transistor P1 is off, and the P-type transistor P2 is on. As a result, the voltage at the output terminal OUT is at the H (i.e., VDD3) level. On the other hand, when the input signal is at the L (i.e., VSS=0 V) level and the inverted version of the input signal is at the H (i.e., VDD) level, the N-type transistor N5 is off, the N-type transistor N6 is on, the P-type transistor P1 is on, and the P-type transistor P2 is off. As a result, the voltage at the output terminal OUT is at the L (i.e., VSS=0 V) level. The level shift circuit shown in FIG. 14, operating in the above-described manner, outputs the signal obtained by level-shifting the input signal at the voltage level of the low-voltage supply VDD to the high-voltage supply VDD3 level.
Nevertheless, if the voltage of the low-voltage supply VDD is set to a low voltage close to the threshold voltage of the N-type transistors N5 and N6, for example, the conventional level shift circuit shown in FIG. 14 does not operate any more. To address this, the threshold voltage of the N-type transistors N5 and N6 is changed to be set to a low voltage of, e.g., 0 V. Then, the conventional level shift circuit of FIG. 14 performs the desired level shifting operation in an excellent manner, even if the voltage of the low-voltage supply VDD is set low.
Now, it will be discussed how the level shift circuit of FIG. 14 operates in the case where the threshold voltage of the N-type transistors N5 and N6 is set to a low voltage. For example, if the input signal is at the L level, the voltage at the drain of the N-type transistor N5 is the voltage of the high-voltage supply VDD3. At this time, the N-type transistor N5 turns off and the potential at a node W3, to which the source of the N-type transistor N5 is connected, is (VDD−threshold voltage). However, if the threshold voltage of the N-type transistor N5 varies to decrease to a negative value due to variations in temperature or variations in the fabrication process, the potential at the node W3 may increase to exceed the voltage of the low-voltage supply VDD. In that case, a current flows from the node W3 via a parasitic diode within the first inverter INV1 into the low-voltage supply VDD, causing an increase in power dissipation.
Another conventional level shift circuit is disclosed in Japanese Laid-Open Publication No. 2001-298356. FIG. 23 illustrates the configuration of this level shift circuit.
The level shift circuit of FIG. 23 performs level shifting of the potential of an input signal powered by a low-voltage supply VDD to the potential of an output signal powered by a high-voltage supply VDD3. The level shift circuit includes: an inverter INV11, which inverts an input signal IN received from an input terminal IN; two N-type transistors N11 and N12, which receive at their respective gates a pair of complementary signals, that is, the input signal IN and the inverted input signal XIN produced from the inverter INV11; a power supply circuit D1 composed of a pair of P-type transistors P11 and P12; and a P-type transistor P13, which operates as a resistor. The power supply circuit D1 supplies the voltage of the high-voltage supply VDD3 to either first or second node W11 or W12 by way of either the P-type transistor P11 or P12.
The level shift circuit further includes a latch circuit E and a disconnecting circuit D2. The latch circuit E includes first and second two-input NAND circuits NAND11 and NAND12, which latch the potentials at the first and second nodes W11 and W12, respectively. The NAND circuit NAND11 is connected at its output side to an output terminal OUT. The disconnecting circuit D2 is composed of a pair of N-type transistors N13 and N14 and disposed in ground paths going from the respective first and second nodes W11 and W12 via the respective N-type complementary-signal-pair-receiving transistors N11 and N12 to the ground, and disconnects the ground paths. The two NAND circuits NAND11 and NAND12 of the latch circuit E are connected at their respective output sides to inverter circuits INV12 and INV13. The inverter circuits INV12 and INV13 function as a power supply control circuit for controlling the power supply circuit D1 and as a disconnection control circuit for controlling the disconnecting circuit D2. Outputs from the inverter circuits INV12 and INV13 are input to the respective gates of the two P-type transistors P11 and P12 of the power supply circuit D1 and to the respective gates of the two N-type transistors N13 and N14 of the disconnecting circuit D2.
In the level shift circuit, the inverter INV11 is composed of a low-voltage device which operates at a low voltage of 1.5 V, for example, supplied from the low-voltage supply VDD. All of the other devices are composed of high-voltage devices which operate at a high voltage of 3.3 V, for example, supplied from the high-voltage supply VDD3.
Next, it will be described how the level shift circuit of FIG. 23 operates. In a steady state, the potentials at the first and second nodes W11 and W12 are both at the H (i.e., VDD3) level. In the case of an input signal at the L (i.e., 0 V) level, the N-type complementary-signal-receiving transistors N11 and N12 are off and on, respectively, and the two outputs (i.e., the respective outputs of the first and second NAND circuits NAND11 and NAND12) from the latch circuit E are at the L (i.e., 0 V) level and at the H (i.e., VDD3) level, respectively, and retain the logic of the respective levels. At this time, the N-type transistors N13 and N14 of the disconnecting circuit D2 are on and off, respectively, and the P-type transistors P11 and P12 of the power supply circuit D1 are off and on, respectively. Since the output of the NAND circuit NAND11 of the latch circuit E is at the L (i.e., 0 V) level, the voltage at the output terminal OUT is at the L (i.e., 0 V) level.
In the above-described state, if the input signal changes from the L (i.e., 0 V) level to the H (i.e., VDD) level, the N-type complementary-signal-receiving transistor N11 turns on. At this time, the N-type transistor N13 of the disconnecting circuit D2 is on, and the potential at the first node W11 changes from the H (i.e., VDD3) level to the L (i.e., 0 V) level, which causes the logic of the latch circuit E to be inverted to the opposite; the output of the NAND circuit NAND11 is inverted to the H (i.e., VDD3) level, while the output of the NAND circuit NAND12 is inverted to the L (i.e., 0 V) level. With this level inversion, the N-type transistor N13 of the disconnecting circuit D2 is turned off, while the P-type transistor P11 of the power supply circuit D1 is turned on, thereby allowing the high-voltage supply VDD3 to precharge the first node W11 to the H (i.e., VDD3) level. On the other hand, the other P-type transistor P12 of the power supply circuit D1 turns off so as to stop precharging of the second node W12 by the high-voltage supply VDD3, while the N-type transistor N14 of the disconnecting circuit D2 turns on so as to connect the second node W12 to the N-type transistor N12 being in the off state, whereby the level shift circuit enters a waiting state in which the level shift circuit waits for the next input signal change. Since the output of the NAND circuit NAND11 of the latch circuit E is at the H (i.e., VDD3) level, the voltage at the output terminal OUT is at the H (i.e., VDD3) level.
Today, in order to reduce power dissipation, for example, there are tendencies to further lower voltage supplied from a power supply. Nevertheless, in the conventional level shift circuit shown in FIG. 23, if the voltage of the low-voltage supply VDD is set to a low voltage close to the threshold voltage of the N-type complementary-signal-receiving high-voltage transistors N11 and N12, it becomes difficult for the N-type complementary-signal-receiving transistors N11 and N12 to operate, causing the level shift circuit to have difficulty in performing the intended operation.
To address this problem, if N-type low-voltage transistors which are capable of withstanding only a low voltage and whose threshold voltage is lower than that of the N-type high-voltage transistors N11 and N12 are employed, the level shift circuit of FIG. 23 can operate as intended, even if the voltage of the low-voltage power supply is set lower than the threshold voltage of the N-type high-voltage transistors N11 and N12.
However, when the conventional level shift circuit shown in FIG. 23 is in the input-signal-change waiting state, the voltage of the high-voltage supply VDD3 at the node W11 or W12 is applied to the drain of either the N-type complementary-signal-receiving transistor N11 or N12 by way of the N-type transistor N13 or N14 being in the on state in the disconnecting circuit D2. Therefore, if these N-type complementary-signal-receiving transistors N11 and N12 are replaced with devices that operate at a low-voltage supplied from the low-voltage supply VDD, these N-type complementary-signal-receiving transistors N11 and N12 will be broken.